1. Field of the Invention
The present invention relates to a method for forming wirings and associated via holes of a semiconductor device, and more particularly to a method for forming wirings by irradiating a laser beam on a metal layer sputtered on an insulating layer formed on a semiconductor substrate, with filling via holes previously provided in the insulating layer with melted material of the metal layer, so that the wirings are electrically well connected with the semiconductor substrate through the via holes.
Recently, since the packing density of semiconductor devices has increased, wirings and associated via holes in the semiconductor device have become microscopic in their dimensions. For example, in the case of very large scale integration (VLSI) semiconductor devices, the smallest portions of the wirings and via holes are smaller than one micrometer (.mu.m).
Usually, wirings of a semiconductor device are formed by patterning a metal layer formed by sputtering electrically conductive material, such as aluminum (Al), onto an insulating layer having a plurality of via holes. In the process of such sputtering, the via holes are filled with the electrically conductive material while the metal layer is being formed on a surface of the insulating layer. However, in such a sputtering process, it has become hard to fill the via holes perfectly since each of the via holes can be so narrow that its diameter becomes smaller than 1 .mu.m and an aspect ratio, which is a ratio of depth to diameter of a hole, is more than one. This results in limiting the fabrication of minute metal layers and via holes. Accordingly, a new method for overcoming the above problem is required.
As one of the new methods, a laser melting method has appeared because the laser melting method is simple in the fabricating process of the semiconductor device, compared with other methods, such as a selective chemical vapor deposition (CVD) method or a bias sputtering method, for planarizing the metal layer. The laser melting method is a method for melting the metal layer by irradiating the layer with a laser beam. And it is expected that when the metal layer is melted by the laser beam, the via holes are sufficiently filled with melted metal while the surface of the metal layer is being planarized. Therefore, the laser melting method will be called the "laser filling method" hereinafter.
2. Description of the Related Art
As mentioned above, in the fabricating process of the semiconductor devices, the laser filling method is new and under development, and there are some reports as to trials of the laser filling method. For example, a report as to the laser filling method was presented by D. B. Tuckerman and A. H. Weisberg in a paper entitled "Planarization of Gold and Aluminum Thin Films Using a Pulsed Laser", in IEEE Electron Device Lett., vol. EDL-7, pp. 1-4, in 1986.
The prior art for planarizing the surface of the metal layer using the laser filling method will be described below, and the problems occurred in the prior art will be discussed referring to FIGS. 1-4.
FIGS. 1(a)-(b) show the general construction of an insulating layer having a via hole, formed on a semiconductor substrate of a semiconductor device such as the VLSI semiconductor device. FIG. 1(a) shows a partial plane view of an insulating layer 2 formed on a semiconductor (silicon (Si)) substrate 1 so as to indicate a via hole 3 which is one of a plurality of via holes provided in the insulating layer 2. FIG. 1(b) shows a cross sectional view along the line A-A' in FIG. 1(a).
In FIG. 1(b), the insulating layer 2 made of silicon dioxide (SiO.sub.2) of 1 .mu.m thickness is deposited on a surface, having a (100) surface orientation, of the semiconductor substrate 1. Then, the via hole 3 is formed in the insulating layer 2 by applying a method combining a photolithography method and an etching method.
The insulating layer 2 can also be made of phosphosilicate glass (PSG) or silicon nitride (Si.sub.3 N.sub.4). A layer combining two layers, such as SiO.sub.2 and PSG or Si.sub.3 N.sub.4 and PSG, also can be used as the insulating layer 2.
After forming the via hole 3 in the insulating layer 2, a sputtered metal layer 4, made of Al for example, is formed on a surface of the insulating layer 2 by applying a sputtering method such as a magnetron sputtering method.
FIGS. 2(a)-(c) show construction of a sputtered metal layer 4 formed on an insulating layer, as an example of the prior art, particularly around a via hole 3. In FIGS. 2(a)-(c), the same reference numerals as in FIGS. 1(a)-(b) designate the same elements as in FIGS. 1(a)-(b). FIG. 2(a) shows a partial plan view of the sputtered metal layer 4 around the via hole 3, and FIG. 2(b) shows a cross sectional view along the line B-B' in FIG. 2(a). As shown in FIGS. 2(a) and 2(b), usually, a size of an aperture of the via hole 3 is relatively large, such as 3 .mu.m. Therefore, the sputtered metal layer 4 can be formed even on a bottom surface 101, which is a partial surface of the semiconductive substrate 1, of the via hole 3, even though a hollow part 41 is produced on a surface of the metal layer 4 at the via hole 3. Accordingly, when the laser filling method is applied to the surface of the sputtered metal layer 4, the hollow part 41 is planarized and so a planarized metal layer 4' can be formed together with perfectly filling the via hole 3 with a melted metal layer, as shown in FIG. 2(c). These details are described in the paper by D. B. Tuckerman and A. H. Weisberg, mentioned above.
However, in the case of very narrow via holes, such that each via hole has a small aperture size such as 1 .mu.m or less, and a high aspect ratio, such as one or more, the thickness of the sputtered metal layer 4 becomes very significant for filling the via holes with the material of the metal layer. FIGS. 3(a)-(c) show a case wherein the sputtered metal layer 4 is too thick, and FIGS. 4(a)-(c) show a case of being too thin. In FIGS. 3 and 4, the same reference numerals as in FIG. 2 designate the same elements as in FIG. 2. Similarly to FIGS. 2(a) and 2(b), FIGS. 3(a) and 4(a) show respectively a partial plan view of the metal layer 4 sputtered on the surface of the insulating layer 2, particularly around a via hole 3, and FIGS. 3(b) and 4(b) show cross sectional views along the line C-C' in FIG. 3(a) and along the line D-D' in FIG. 4(a) respectively.
When the sputtered metal layer 4 is too thick compared with a small aperture size of the narrow via hole 3, a part of the sputtered metal layer 4 formed around the aperture of the via hole 3 becomes thick so that the aperture is almost closed, as shown by a portion 42 in FIGS. 3(a) and 3(b). Therefore, when the laser filling method is applied to the surface of the sputtered metal layer 4 for the planarization, the melted metal layer happens to close the portion 42 completely, which produces a cave 43 in the via hole 3 as shown in FIG. 3(c). This results in increasing resistance at the via hole 3. This cave formation is characteristic to the laser filling of submicron via holes. About this cave 43, Tuckerman says nothing. The reasons why the case 43 is produced are that: (1) the sputtered metal layer is too thick; (2) each via hole has an aperture size which is too small and an aspect ratio which is too high; and (3) the viscosity of the melted metal is too large when the sputtered metal layer is melted by the laser beam irradiation.
When sputtered metal layer 4 is too thin, only poor metal material is formed on inside and bottom walls of the via hole 3, as shown in FIG. 4(b). Therefore, when the laser filling method is applied to the sputtered metal layer 4, a part of the melted metal layer happens to be torn off the insulating layer 2, as shown by a portion 44 in FIG. 4(c). This tearing phenomenon occurs because the thin sputtered metal layer 4 is melted by the laser beam. Since the thickness of the layer 4 is too thin, the quantity of the melted metal is insufficient for filling the via hole 3 and maintaining a flat surface of the melted metal against its surface tension. This results in completely cutting off the electrical contact between the planarized metal layer 4' and the semiconductor substrate 1 through the via hole 3. When this tearing phenomenon occurs, additional electrically conductive material must be deposited on the planarized metal layer 4' for repairing the torn portion 44 so as to reform the connection.